Referring to FIG. 12, which is a cross sectional view of a conventional lateral MOSFET, an n-type well 2 is formed in the surface portion of a p-type semiconductor substrate 1. A p-type well 3 is formed selectively in the surface portion of n-type well 2. An n+-type source region 4 and a p+-type contact region 5 are formed in the surface portion of the p-type well 3. A source electrode 10 is in contact with both the p+-type contact region 5 and the n+-type source region 4. An n+-type drain region 8 is formed in the surface portion of the n-type well 2 and spaced apart from the p-type well 3. A drain electrode 11 is in contact with the n+-type drain region 8.
A portion (extended) of the p-type well 3 extends between the n+-type source region 4 and the n-type well 2 so that the n+-type source region 4 is spaced apart from the n-type well 2. A gate electrode 7 is above the extended portion of p-type well 3 with a gate oxide film 6 interposed therebetween. The gate oxide film 6 and the gate electrode 7 extend to the vicinity of the n+-type drain region 8. A LOCOS oxide film 9 is formed on a portion (sandwiched) of the n-type well 2, sandwiched between the portion of the gate electrode 7 on the drain side and the n+-type drain region 8 for relaxing the electric field in the sandwiched portion of the n-type well 2 beneath the gate electrode 7. A similar LOCOS oxide film 19 is formed adjacent to the p+-type contact region 5 and the p-type well 3, extending in the opposite direction (straddling the n-type well 2 and outside the same). A back electrode 12 is formed on the back surface of the p-type semiconductor substrate 1. Usually, the back electrode 12 is biased at the same potential as the source electrode 10.
When a voltage lower than the threshold voltage is applied to the gate electrode 7, in the state where a voltage positive with respect to the potential of the source electrode 10 is applied to the drain electrode 11, no current flows in the MOSFET having the structure shown in FIG. 12 since the pn-junction between the p-type well 3 and the n-type well 2 is biased in reverse. In contrast, when a voltage higher than the threshold voltage is applied to the gate electrode 7, an inversion layer is formed in the surface portion of the p-type well 3 beneath the gate electrode 7. Since current flows from the n+-type drain region 8 to the n+-type source region 4 via the n-type well 2 and the inversion layer formed in the surface portion of the p-type well 3, the well known MOSFET switching operations can be carried out.
Since the p-type well 3 and the p-type semiconductor substrate 1 are spaced apart for the n-type well 2, the MOSFET having the structure described above is applicable to the high-side switching, in which the potentials of the n+-type source region 4 and the p-type well 3 become high in the ON-state of the MOSFET. To improve the tradeoff relation between the breakdown voltage and the ON-voltage in the lateral MOSFET having the structure described above, it is effective to employ a reduced surface field structure (hereinafter referred to as a “RESURF structure”). In applying the RESURF structure, the total impurity amount per unit area in the n-type well 2 is set around 1×1012 cm−2, which is known as the RESURF condition.
A semiconductor device having the following structure is known to those skilled in the art. The known semiconductor device is a lateral MOSFET including an n−-type epitaxial layer grown on a p-type semiconductor substrate, a p-type body region formed in the n−-type epitaxial layer, a p+-type channel region formed in the body region, an n+-type source region formed in the body region, an n+-type drain region formed in the epitaxial layer such that the drain region is spaced apart from the channel region, a gate electrode above the portion of the epitaxial layer between the source region and the drain region as well as above the p-type channel region with a gate oxide film interposed therebetween, and an n+-type buried region beneath the body region. See for instance, JP P Hei. 11 (1999)-102982 A (FIG. 1).
Another semiconductor device having the following structure is known to those skilled in the art. This semiconductor device is a MOSFET exhibiting a high breakdown voltage. It includes a p-type semiconductor substrate, a p-type body layer formed selectively in the surface portion of the semiconductor substrate, an n+-type source layer formed selectively in the surface portion of the body layer, an n−-type first offset layer formed selectively in the other surface portion of the semiconductor substrate different from the surface portion, in which the body layer is formed, an n−-type second offset layer formed selectively in the surface portion of the first offset layer, an n+-type drain layer formed selectively in the surface portion of the second offset layer, a gate electrode above the portion of the body layer extending between the source layer and the first offset layer with a gate insulator film interposed therebetween, a source electrode in contact with the body layer surface and the source layer surface, and a drain electrode on the drain layer. See for example JP P Hei. 11 (1999)-121742 A (FIG. 1).
Still another semiconductor device having the following structure is known to those skilled in the art. This known semiconductor device is a lateral MOSFET including a substrate, including an n-type semiconductor layer, a p-type base region formed in the surface portion of the semiconductor layer, an n+-type source region in the surface portion of the p-type base region, an n+-type drain region arranged in the surface portion of the semiconductor layer such that the drain region is spaced apart from the base region, the portion of the base region between the source region and the drain region being a channel region, a gate insulator film on the channel region, a gate electrode on the gate insulator film, a source electrode connected to the source region, and a drain electrode connected to the drain region. This lateral MOSFET further includes an n-type region in the surface portion of the semiconductor layer between the drain region and the base region, the n-type region being doped more heavily than the semiconductor layer, and the portion of the n-type region closer to the drain region being doped more heavily. See for instance JP P 2001-352070 A (FIGS. 1 and 2).
In the conventional lateral MOSFET having the structure shown in FIG. 12, the impurity concentration in the portion of the n-type well 2 in the vicinity of the junction between the p-type well 3 and the n-type well 2 is very low due to the diffusion for forming the p-type well 3. In growing the LOCOS oxide film 9 after forming the n-type well 2, boron atoms used typically for a p-type impurity in the p-type semiconductor substrate 1 are extracted to grow the LOCOS oxide film. Due to the boron extraction, the net n-type impurity concentration of the n-type well under the LOCOS oxide film 9 rises and the impurity concentration gradient becomes especially steep, as illustrated in FIG. 13(b), from the vicinity of the junction between the p-type well 3 and the n-type well 2 to the source-side end of the LOCOS oxide film 9. The structure near the Si surface from the p-type well 3 to the source-side end of LOCOS oxide film 9 is schematically shown in FIG. 13(a). The impurity concentration profile across the structure shown in FIG. 13(a) is illustrated FIG. 13(b).
The electric field strength profile around the avalanche voltage under the RESURF conditions, under which the depletion layer expanding from the junction between the n-type well 2 and the p-type semiconductor substrate 1 (see FIG. 12) and the depletion layer expanding from the junction between the n-type well 2 and the p-type well 3 are brought into contact with each other at the impurity concentration profile as illustrated in FIG. 13(b), and the lateral expansions of the depletion layers are enhanced (RESURF effects), as shown in FIG. 13(c). As shown FIG. 13(c), the electric field strength is low in the vicinity of the junction between the n-type well 2 and the p-type well 3. The electric field strength exhibits the maximum in the vicinity of the source-side end of the LOCOS oxide film 9, at which the impurity concentration becomes high sharply. When the impurity concentration in the n-type well 2 is low, the electric field strength exhibits the maximum in the vicinity of the drain-side end of the LOCOS oxide film 9.
Since the electric field strength exhibits the maximum value in the vicinity of the source-side end of the LOCOS oxide film 9, the component, sustained between the p-type well 3 and the source-side end of the LOCOS oxide film 9, of the voltage expressed by the integration of the electric field strength is low. When the impurity concentration in the portion of the n-type well 2 between the p-type well 3 and the source-side end portion of the LOCOS oxide film 9 is low, the electrons flowing from the channel region, formed in the surface portion of the p-type well 3 beneath the gate electrode 7 by applying a voltage higher than the threshold voltage to the gate, into the n-type well 2 are liable to subject to the JFET effects. Therefore, the ON-resistance rises and the tradeoff relation between the breakdown voltage and the ON-resistance becomes worse. Since it is necessary to lower the impurity concentration in the n-type well 2 when the RESURF effects are not utilized, the ON-resistance rise by the JFET effects becomes more remarkable. Since the electric field strength beneath the gate-side end portion of the LOCOS oxide film 9 becomes very high when the n-type well 2 is doped heavily, the breakdown voltage is impaired. Therefore, it is not desirable to heavily dope the n-type well 2.
When the lateral MOSFET having the structure shown in FIG. 12 is used for a high-side switch, the following problems can occur. FIG. 14 is an equivalent circuit diagram showing a general connection example of a high-side switch using a MOSFET. As shown in FIG. 14, the drain terminal (D) of a MOSFET 21 is connected to a power supply and the source terminal (S) thereof to a load 22. The source potential in the ON-state of the MOSFET 21 is almost Vdd (≈Vdd−ON-voltage of the MOSFET).
FIG. 15 is a cross sectional view describing the depletion layer expansion in the ON-state of the lateral MOSFET used for a high-side switch. In the ON-state of the MOSFET 21, a depletion layer is expanded from the pn-junction between the n-type well 2 and the p-type semiconductor substrate 1 by the voltage applied between drain the electrode 11 and the back electrode 12 (Vdd (the drain voltage)−GND (the ground potential)). As the applied voltage becomes higher, the depletion layer expanding from the pn-junction between the n-type well 2 and the p-type semiconductor substrate 1 is connected to the depletion layer expanding from the pn-junction between the p-type well 3 and the n-type well 2. Further, a punch-through phenomenon can occur, by which current IPT is made to flow from the p-type well 3 to the p-type semiconductor substrate 1. Since the current IPT flows bypassing the load 22, the current IPT causes an invalid current. Therefore, it does not attain the primary purpose of making a current flow through the load 22.
Although the punch-through voltage depends on the impurity concentration gradient in the n-type well 2, the punch-through voltage is higher fundamentally as the total impurity amount in the portion of the n-type well 2 beneath the p-type well 3 is higher and as the substantial thickness of the n-type well 2 is larger. Here, the substantial thickness of the n-type well 2 is the thickness of the remaining portion of the n-type well 2 remaining after subtracting the portion, the conductivity type thereof is inverted by the p-type well 3, from the n-type well 2. When the n-type well 2 is under the RESURF condition, the net total impurity amount per unit area in the n-type well 2 is around 1×1012 cm−2. However, the total impurity amount in the portion of the n-type well 2 beneath the p-type well 3 is reduced greatly, since the n-type impurity in this portion of the n-type well 2 is canceled by the p-type impurity in the p-type well 3. The remaining thickness of the n-type well 2 beneath the p-type well 3 is also reduced.
Since the heavily doped portion near the surface of the n-type well 2 is canceled by the p-type well 3 especially when the n-type well 2 is formed by diffusion, the total impurity concentration and the thickness of the n-type well 2 are reduced remarkably. Although these troubles can be obviated by elongating the diffusion depth of the n-type well 2, it is necessary to conduct diffusion treatment at a high temperature for a long time. Since there exists a certain time limit for obtaining the diffusion depth of the n-type well 2 described above, it is difficult to attain the desired improvements. Since the p-type well 3 and the p-type semiconductor substrate 1 are biased at the same potential when the MOSFET described above is used for a low-side switch, however, the above-described troubles can be avoided.
There still remains a need to obviate the problems described above, and improve the tradeoff relation between the breakdown voltage and the ON-voltage. There also remains a need to provide a semiconductor device that exhibits a high punch-through voltage suitable for a high-side switch. The present invention addresses these needs.